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| WM2632 Octal 8-bit, Serial Input, Voltage Output DAC with Internal Reference Production Data, April 2001, Rev 1.1 FEATURES * * * * * * * * * Eight 8-bit DACs in one package Dual supply 2.7V to 5.5V operation DNL 0.1 LSBs, INL 0.3 LSBs typical Programmable settling time / power (1.0s typical in fast mode) Internal programmable voltage reference Microcontroller compatible serial interface Power down mode ( < 0.1A) Monotonic over temperature Data output for daisy chaining DESCRIPTION The WM2632 is an octal, 8-bit, resistor string digital-toanalogue converter. The eight individual DACs contained in the IC can be switched in pairs between fast and slow (low power) operation modes, or powered down, under software control. Alternatively, the whole device can be powered down, reducing current consumption to less than 0.1A. The DAC outputs are buffered by a rail-to-rail amplifier with a gain of two, which is configurable as Class A (fast mode) or Class AB (for low-power mode). The WM2632 has been designed to interface directly to industry standard microprocessors and DSPs, and can operate on two separate analogue and digital power supplies. It is programmed with a 16-bit serial word comprising 4 address bits and up to 12 DAC or control register data bits. All eight DACs can be simultaneously forced to a preset value using a preset input pin. A daisy-chain data output makes it possible to control several of Wolfson's octal DACs from the same interface, without increasing the number of control lines. The device is available in a 20-pin TSSOP package. Commercial temperature (0 to 70C) and Industrial temperature (-40 to 85C) variants are supported. APPLICATIONS * * * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated / remote industrial controls Programmable loop controllers CNC machine tools Machine and motion control devices Wireless telephone and communication systems Robotics ORDERING INFORMATION DEVICE WM2632CDT WM2632IDT TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 20-pin TSSOP 20-pin TSSOP BLOCK DIAGRAM REF (16) AVDD (11) DVDD (20) TYPICAL PERFORMANCE 0.04 1.024V / 2.048V SELECTABLE REFERENCE 0.03 Differential Non-Linearity (LSBs) 0.02 0.01 DAC A DIN (2) SCLK (3) FS (4) MODE (17) PREB (5) DOUT (19) REF SERIAL INTERFACE AND CONTROL LOGIC LATCH POWER/SPEED CONTROL RESISTOR STRING 0 (12) OUT A -0.01 -0.02 -0.03 -0.04 0 32 64 96 128 DIGITAL CODE 160 192 224 256 DACs B, C, D, E, F, G, H as DAC A (6-9, 13-15) OUT B to H LOADB (18) AGND (10) DGND (1) WOLFSON MICROELECTRONICS LTD Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions. 2001 Wolfson Microelectronics Ltd. WM2632 PIN CONFIGURATION DGND DIN SCLK FS PREB OUTE OUTF OUTG OUTH AGND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DVDD DOUT LOADB MODE REF OUTD OUTC OUTB OUTA AVDD Production Data PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME DGND DIN SCLK FS PREB OUTE OUTF OUTG OUTH AGND AVDD OUTA OUTB OUTC OUTD REF MODE LOADB DOUT DVDD TYPE Supply Digital input Digital input Digital input Digital input Analogue output Analogue output Analogue output Analogue output Supply Supply Analogue output Analogue output Analogue output Analogue output Analogue I/O Digital input Digital input Digital output Supply Digital Ground Digital serial data input Serial clock input Frame sync input Preset input DAC Output E DAC Output F DAC Output G DAC Output H Analogue Ground Analogue positive power supply DAC Output A DAC Output B DAC Output C DAC Output D Voltage reference input / output Input mode Load DAC Serial data output Digital positive power supply DESCRIPTION WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 2 Production Data WM2632 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Digital supply voltages, AVDD or DVDD to GND Reference input voltage Digital input voltage range to GND Operating temperature range, TA Storage temperature Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds WM2632CDT WM2632IDT -0.3V -0.3V 0C -40C -65C MIN MAX 7V AVDD + 0.3V DVDD + 0.3V 70C 85C 150C 260C RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF Output Load Resistance Load capacitance Operating free-air temperature SYMBOL AVDD, DVDD VIH VIL VREF RL CL TA AVDD = 5V AVDD = 3V TEST CONDITIONS MIN 2.7 2 GND GND 2 WM2632CDT WM2632IDT 0 -40 100 70 85 2.048 1.024 0.8 AVDD AVDD TYP MAX 5.5 UNIT V V V V k pF C C Note: Reference input voltages greater than AVDD/2 will cause saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 3 WM2632 ELECTRICAL CHARACTERISTICS Production Data Test Characteristics: RL = 10k, CL = 100pF AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error DC power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH=DVDD, VIL=0V AVDD = DVDD = 5V, VREF = 2.048V Slow Fast See Note 8 No load, all inputs 0V or DVDD DAC code 10%-90% Load = 10k, 100pF Fast Slow See Note 9 DAC code 10%-90% Load = 10k, 100pF Fast Slow See Note 10 DAC code 127 to 128 10kHz sine wave, 4V pk-pk 10k Load 2k to 10k load See Note 7 0 AVDD-0.4 0.3 V % Full Scale INL DNL ZCE GE PSRR Code 6 to 255 (see Note 1) Code 6 to 255 (see Note 2) See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 -50 30 10 8 0.3 0.1 1 1 30 0.6 bits LSB LSB mV % FSR dB V/C ppm/C SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 6 16 0.1 8 21 mA mA A Power down supply current Dynamic DAC Specifications Slew rate 4 1 10 3 V/s V/s Settling time 1 3 4 -90 3 7 s s nV-s dB Glitch energy Channel Crosstalk WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 4 Production Data WM2632 Test Characteristics: RL = 10k, CL = 100pF AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Reference Configured as Input Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREF CREF VREF=2VPP at 1kHz + 2.048V DC, DAC code 0 VREF= 0.4VPP + 2.048V DC, DAC code 128 Slow Fast VREFOUTL VREFOUTH IREFSRC IREFSNK in parallel with 100nF cap. -1 1 10 60 VDD > 4.75V 1.010 2.020 50 10 -84 k pF dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 1.9 2.2 1.024 2.048 1.040 2.096 1 MHz MHz V V mA mA F dB A A pF Reference Configured as Output Low reference voltage High reference voltage Output source current Output sink current Load Capacitance PSRR Digital Inputs High level input current Low level input current Input capacitance Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing a digital code of 128 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates. 10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. IIH IIL CI Input voltage = DVDD Input voltage = 0V -1 -1 8 1 1 WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 5 WM2632 SERIAL INTERFACE Production Data tWL SCLK X tSUD DIN DOUT X X D15 D15 * 1 2 tHD D14 D14 * tWH 3 4 16 X D13 D13 * 2 D12 * D1 D1 * D0 D0 * tSUC16-FS X X tWHFS tSUFSCLK FS (C MODE) tWLFS FS (DSP MODE) * DIN data from previous word (delayed by 16 clock cycles) No high to low transitions Figure 1 Timing Diagram SYMBOL tSUFSCLK tC16-FS tWLOADB tWH tWL tSUD tHD tWHFS tWLFS ts TEST CONDITIONS Setup time, FS pin low before first falling edge of SCLK Setup time, 16th falling clock edge after FS low to rising edge of FS (only used in microcontroller mode) Pulse duration, LOADB low Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge Pulse duration, FS high Pulse duration, FS low DAC Output settling time MIN 8 10 10 16 16 8 5 10 10 TYP MAX UNIT ns ns ns ns ns ns ns ns ns see Dynamic DAC Specifications WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 6 Production Data WM2632 TYPICAL PERFORMANCE GRAPHS 0.3 0.2 Integral Non-Linearity (LSBs) 0.1 0 -0.1 -0.2 -0.3 0 32 64 96 128 DIGITAL CODE 160 192 224 256 Figure 2 Integral Non-Linearity 1 VDD = 3.3V VREF = 1.024V Input Code = 0 Slow Fast 1 VDD = 5V VREF = 2.048V Input Code = 0 Slow Fast 0.8 0.8 Output Voltage (V) Output Voltage (V) 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 0.5 1 Sink Current (mA) 1.5 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Sink Current (mA) Figure 3 Output Load Regulation (Sink) AVDD = 3V Figure 4 Output Load Regulation (Sink) AVDD = 5V 2.1 VDD=3V VREF=1.024V Input Code = 4095 4.15 Slow Fast 4.13 VDD=5V VREF=2.048V Input Code = 4095 Slow Fast 2.08 DACA (Volts) 2.06 DACA (Volts) 4.11 2.04 4.09 2.02 4.07 2 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 4.05 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 Sourcing Current (mA) Sourcing Current (mA) Figure 5 Output Load Regulation (Source) AVDD = 3V Figure 6 Output Load Regulation (Source) AVDD = 5V WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 7 WM2632 DEVICE DESCRIPTION GENERAL FUNCTION Production Data The WM2632 is an octal 8-bit, voltage output DAC. It contains a serial interface, control logic for speed and power down, a programmable voltage reference, and eight digital to analogue converters. Each converter uses a resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2 VREF INPUT 1111 : 1000 0001 1111 ( ) CODE 256 OUTPUT 2 VREF ( ) 255 256 : 2 VREF ( ) 129 256 256 REF 1000 0000 2 VREF ( ) 128 = V 2 VREF 0111 : 0000 0000 1111 ( ) 127 : 256 1 256 0001 0000 2 VREF () 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance. PROGRAMMABLE REFERENCE The DAC reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 8 Production Data WM2632 SERIAL INTERFACE INTERFACE MODES The control interface can operate in two different modes: * In the microcontroller mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS. In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16th falling clock edge. * SCLK FS DIN X D15 D14 D1 D0 X E15 E14 E1 E0 X X F15 F14 Figure 7 Interface Timing in Microcontroller Mode SCLK FS DIN X D15 D14 D1 D0 E15 E14 E1 E0 X X X F15 F14 Figure 8 Interface Timing in DSP Mode The operating mode is selected using pin 17 (MODE). MODE PIN (17) HIGH LOW or unconnected INTERFACE MODE Microcontroller DSP mode Table 2 Interface Mode Selection SERIAL CLOCK AND UPDATE RATE Figure 1 shows the interface timing. The maximum serial clock rate is: f SCLK max = 1 = 31MHz tWH min + tWL min Since a data word contains 16 bits, the sample rate is limited to f s max = 16(tWH min + tWL min ) 1 = 1.95MHz However, the DAC settling time to 8 bits accuracy limits the response time of the analogue output for large input step transitions. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 9 WM2632 DAISY CHAINING MULTIPLE DEVICES Production Data The DOUT output (pin 19) provides the data sampled on DIN with a delay of 16 clock cycles. This signal can be used to control another WM2632 or similar device in a daisy-chain type circuit. DIN SCLK FS LOADB DOUT DIN SCLK FS LOADB DIN SCLK FS LOADB DOUT OCTAL DAC #1 OCTAL DAC #2 OCTAL DAC #3 Figure 9 Daisy Chaining SOFTWARE CONFIGURATION OPTIONS DATA FORMAT The WM2632 is controlled with a 16-bit code consisting of four address bits, A0-A3, and 12 data bits. D15 A3 D14 A2 D13 A1 D12 A0 D11 D10 D9 D8 D7 D6 Data D5 D4 D3 D2 D1 D0 Table 3 Input Data Format Using the four address bits, 16 different registers can be addressed. A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 4 Register Map A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 REGISTER DAC A Code DAC B Code DAC C Code DAC D Code DAC E Code DAC F Code DAC G Code DAC H Code Control Register 0 Control Register 1 Preset all DACs RESERVED DAC A and complement B DAC C and complement D DAC E and complement F DAC G and complement H WOLFSON MICROELECTRONICS LTD DIN SCLK FS LOADB DOUT PD Rev 1.1 April 2001 10 Production Data WM2632 DAC A TO H CODE REGISTERS Addresses 0 to 7 are the DAC registers. Bits D11 (MSB) to D4 (LSB) from these registers are transferred to the respective DAC when the LOADB input (pin 18) is low. Bits D3 to D0 are unused and must be set to 0. For instantaneous updating, LOADB can be held low permanently. CONTROL REGISTER 0 Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power Down and Data Input Format. BIT Function Default D11 X X D10 X X D9 X X D8 X X D7 X X D6 X X D5 X X D4 PD 0 D3 DO 0 D2 R1 0 D1 R0 0 D0 IM 0 Table 5 Control Register 0 Map BIT PD DO R1 R0 IM X DESCRIPTION Full device Power Down DOUT Enable Int / Ext Reference Select Internal Reference Select Input Mode Reserved 0 Normal Disabled External 1.024V Straight Binary 1 Power Down Enabled Internal 2.048V Two's Complement Table 6 Control Register 0 Functionality CONTROL REGISTER 1 Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of the device. The settling time in fast mode is typically 1s. In slow mode, the settling time is typically 3s and power consumption is reduced. BIT Function Default D11 X X D10 X X D9 X X D8 X X D7 PGH 0 D6 PEF 0 D5 PCD 0 D4 PAB 0 D3 SGH 0 D2 SEF 0 D1 SCD 0 D0 SAB 0 Table 7 Control Register 1 Map BIT PXY SXY DESCRIPTION Power Down DACs X and Y Speed Setting for DACs X and Y 0 Normal Slow 1 Power Down Fast Table 8 Control Register 1 Functionality DAC PRESET REGISTER The Preset register (address 10) makes it possible to update all eight DACs at the same time. The value stored in this register becomes the digital input to all the DACs when the asynchronous PREB input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are set to zero scale. TWO-CHANNEL REGISTERS The two-channel registers (addresses 12 to 15) provide a `differential output' function where writing data to one DAC will automatically write the complement to the other DAC in the pair. For example, writing a value of 255 to address 12 will set DAC A to full scale and DAC B to zero scale. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 11 WM2632 PROGRAMMABLE INTERNAL REFERENCE Production Data The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10M and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 0 0 1 1 REF0 0 1 0 1 REFERENCCE External (default) 1.024V 2.048V External Table 9 Programmable Internal Reference APPLICATIONS INFORMATION LINEARITY, OFFSET, AND GAIN ERROR Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 10. Output Voltage 0V Negative Offset DAC code Figure 10 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (nonzero) output voltage. POWER SUPPLY DECOUPLING AND GROUNDING Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1F decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 12 Production Data WM2632 PACKAGE DIMENSIONS DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) DM008.D b 20 e 11 E1 E GAUGE PLANE 1 10 D 0.25 c A A2 A1 -C0.1 C SEATING PLANE L Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 6.40 4.30 0.45 o 0 Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153 MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 o 8 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 13 |
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